Definite Asynchronous Sequential Circuits

An asynchronous unit delay is an n input n output of the input n-tuple prior to the last inlput change. It asynchronous sequential circuit in which the present value of the will then be shown that every asynchronous definite flow output n-tuple is equal to the value of the input n-tuple prior to the last input change. This paper considers the problem of determining ablecan brizeday a fee bac r onnetiono when a fundamental mode flow table is realizable as a feedback-free asynchronous unit delays and combinational gates, and connection of asynchronous unit delays. It is shown that such a that every feedback-free circuit of delays and gates has realization exists if and only if the flow table is asynchronous a definite table. Thus the relation of definite tables to definite, where the asynchronous definite property is a modification feedback-free circuits in synchronous theory has a very of the definite property of synchronous sequential machines. A close analogy in the asynchronous case, if the proper straightforward method of realizing asynchronous definite flow closetationis u se,r tables without critical races by feedback-free circuits of asynchronous interpretation is used. unit delays and combinational gates is developed. The use of asynAside from the fact that synchronous and asynchrochronous unit delays for definite tables avoids complicated secondary nous theories are brought closer together by this point assignment problems, results in circuits with very simple structure, of view, there are other advantages of considering asynand brings closer the theories of synchronous and asynchronous c chronous definite machines and their realizations using sequential machines. asynchronous delays.